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com:basic_i2c [2025/05/31 22:43] – [lamaPLC Communication: I²C] vamsan | com:basic_i2c [2025/05/31 22:45] (current) – vamsan | ||
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**I²C** (// | **I²C** (// | ||
- | I²C is a common digital communication standard used in various products. The protocol uses a two-wire communication interface, allowing multiple controllers and target peripheral devices. This application note describes many important | + | I²C is a common digital communication standard used in various products. The protocol uses a two-wire communication interface, allowing multiple controllers and target peripheral devices. This application note describes many important protocol |
This application note discusses the protocol and the physical layer for I²C communications. Because I²C is often used with data converter devices, examples of communications were provided for a DAC and an ADC to write and read from registers. | This application note discusses the protocol and the physical layer for I²C communications. Because I²C is often used with data converter devices, examples of communications were provided for a DAC and an ADC to write and read from registers. | ||
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There are several other similar protocols discussed in the I²C specifications. Advanced Telecommunications Computing Architecture (ATCA) is a follow-on to Compact PCI used in rack-mounted telecom hardware. | There are several other similar protocols discussed in the I²C specifications. Advanced Telecommunications Computing Architecture (ATCA) is a follow-on to Compact PCI used in rack-mounted telecom hardware. | ||
- | Display Data Channel (DDC) is a monitor or display information protocol | + | Display Data Channel (DDC) is a monitor or display information protocol |
I²C is similar in concept to [[com: | I²C is similar in concept to [[com: | ||
===== I²C specifications ===== | ===== I²C specifications ===== | ||
* In the most common case, the I²C bus contains only one master, but the possibility of a multimaster is also not excluded | * In the most common case, the I²C bus contains only one master, but the possibility of a multimaster is also not excluded | ||
- | * I²C uses an open-ended pair of wires for data transfer, the serial data line (SDA) and the serial clock signal (SCL). The two wires must be pulled to the operating voltage with resistors, the wires typically operate with a voltage of 5V or 3.3V, but a different voltage specification is also not excluded. | + | * I²C uses an open-ended pair of wires for data transfer: the serial data line (SDA) and the serial clock signal (SCL). The two wires must be pulled to the operating voltage with resistors. The wires typically operate with a voltage of 5V or 3.3V, but a different voltage specification is also not excluded. |
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===== Open-Drain Connection ===== | ===== Open-Drain Connection ===== | ||
- | The open-drain connections are used on both SDA and SCL lines and connect to an NMOS transistor. This open-drain connection controls the I2C communication line and pulls the line low or releases the line high. The open-drain refers to the NMOS bus connection when the NMOS is turned OFF. Next pics shows the open-drain connection as the NMOS is turned on: | + | The open-drain connections are used on both SDA and SCL lines and connect to an NMOS transistor. This open-drain connection controls the I2C communication line and pulls the line low or releases the line high. The open-drain refers to the NMOS bus connection when the NMOS is turned OFF. The next pic shows the open-drain connection as the NMOS is turned on: |
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- | To set the voltage level of the SDA or SCL line, the NMOS is set on or off. When the NMOS is on, the device pulls current through the resistor to ground. This pulls the open-drain line low. Typically, the transition from high to low for I²C is a fast transition | + | The NMOS is set on or off to set the voltage level of the SDA or SCL line. When the NMOS is on, the device pulls current through the resistor to ground, pulling |
- | When the NMOS turns off, the device stops pulling current, and the pullup | + | When the NMOS turns off, the device stops pulling current, and the pull-up |
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===== I²C addresses ===== | ===== I²C addresses ===== | ||
- | Different manufacturers' | + | Different manufacturers' |
===== I²C Arduino ===== | ===== I²C Arduino ===== | ||
- | The I²C protocol | + | The I²C protocol |
- | In I²C, there is one controller device, with one or more peripheral devices connected to the controllers | + | In I²C, one controller device |
- | As the clock line changes from low to high (known as the rising edge of the clock pulse), a single bit of information is transferred from the board to the I²C device over the SDA line. As the clock line keeps pulsing, more and more bits are sent until a sequence of a 7 or 8 bit address, and a command or data is formed. When this information is sent - bit after bit -, the called upon device executes the request and transmits | + | As the clock line changes from low to high (known as the rising edge of the clock pulse), a single bit of information is transferred from the board to the I²C device over the SDA line. As the clock line keeps pulsing, more and more bits are sent until a sequence of a 7 or 8-bit address, and a command or data is formed. When this information is sent - bit after bit -, the called upon device executes the request and transmits |
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* The controller sends out instructions through the I2C bus on the data pin (SDA), and the instructions are prefaced with the address, so that only the correct device listens. | * The controller sends out instructions through the I2C bus on the data pin (SDA), and the instructions are prefaced with the address, so that only the correct device listens. | ||
* Then there is a bit signifying whether the controller wants to read or write. | * Then there is a bit signifying whether the controller wants to read or write. | ||
- | * Every message needs to be acknowledged, to combat unexpected results, once the receiver has acknowledged the previous information it lets the controller know, so it can move on to the next set of bits. | + | * Every message needs to be acknowledged to combat unexpected results. Once the receiver has acknowledged the previous information, it lets the controller know so it can move on to the next set of bits. |
* 8 bits of data | * 8 bits of data | ||
* Another acknowledgement bit | * Another acknowledgement bit | ||
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- | According to the analysis of Texas Instruments, | + | According to the analysis of Texas Instruments, |
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- | For this case, they recommend using the [[: | + | They recommend using the [[: |